MT49H8M36FM-25

Product Summary

The MT49H8M36FM-25 is a high-speed memory device. The MT49H8M36FM-25 is designed for high bandwidth data storage—telecommunications, networking, and cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high speed operation. The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output data is referenced to the free-running output data clock. Commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data clock(s). Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is programmable from 2, 4, or 8 by setting the mode register. The MT49H8M36FM-25 is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers. Bank-scheduled refresh is supported with the row address generated internally. The MT49H8M36FM-25 package is used to enable ultra high-speed data transfer rates and a simple upgrade path from early generation devices.

Parametrics

MT49H8M36FM-25 absolute maximum ratings: (1)I/O voltage: –0.3, VDDQ + 0.3 V; (2)Voltage on VEXT supply relative to VSS: –0.3, +2.8 V; (3)Voltage on VDD supply relative to VSS: –0.3, +2.1 V; (4)Voltage on VDDQ supply relative to VSS: –0.3, +2.1 V.

Features

MT49H8M36FM-25 features: (1) 144-ball μBGA package; (2) HSTL I/O (1.5V or 1.8V nominal); (3) 25–60Ω matched impedance outputs; (4) 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O; (5) On-die termination (ODT)RTT; (6) Reduced cycle time (20ns at 400 MHz); (7) Nonmultiplexed addresses (address multiplexing option available); (8) SRAM-type interface; (9) Programmable READ latency (RL), row cycle time, and burst sequence length; (10) Balanced READ and WRITE latencies in order to optimize data bus utilization; (11) Data mask for WRITE commands; (12) Differential input clocks (CK, CK#); (13) Differential input data clocks (DKx, DKx#); (14) On-die DLL generates CK edge-aligned data and output data clock signals; (15) Data valid signal (QVLD).

Diagrams