Product Summary

The MT49H32M18FM-25E:A is a RLDRAM. It is a high-speed memory device designed for high bandwidth data storage-telecommunications, networking, and cache applications, etc. The MT49H32M18FM-25E:A is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers. The μBGA 144-ball package is used to enable ultra high-speed data transfer rates and a simple upgrade path from early generation devices. The MT49H32M18FM-25E:A’s 8-bank architecture is optimized for sustainable high speed operation.

Parametrics

MT49H32M18FM-25E:A absolute maximum ratings: (1)I/O voltage:–0.3V to Vddq + 0.3V; (2)Voltage on Vext supply relative to Vss:–0.3V to +2.8V; (3)Voltage on Vdd supply relative to Vss:–0.3V to +2.1V; (4)Voltage on Vddq supply relative to Vss:–0.3V to +2.1V.

Features

MT49H32M18FM-25E:A features: (1)533 MHz DDR operation (1.067 Gb/s/pin data rate); (2)38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency); (3)Organization: 64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O, 8 banks; (4)Reduced cycle time (15ns at 533 MHz); (5)Nonmultiplexed addresses (address multiplexing option available); (6)SRAM-type interface; (7)Programmable READ latency (RL), row cycle time, and burst sequence length; (8)Balanced READ and WRITE latencies in order to optimize data bus utilization; (9)Data mask for WRITE commands; (10)Differential input clocks (CK, CK#); (11)Differential input data clocks (DKx, DKx#); (12)On-die DLL generates CK edge-aligned data and output data clock signals; (13)Data valid signal (QVLD); (14)144-ball μBGA package; (15)HSTL I/O (1.5V or 1.8V nominal); (16)25–60Ω matched impedance outputs; (17)2.5V Vext, 1.8V Vdd, 1.5V or 1.8V Vddq I/O; (18)On-die termination (ODT) Rtt.

Diagrams

MT49H32M18FM-25E:A block diagram

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