Product Summary

The MT48H8M32LFB5-75 IT:G Mobile SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. The MT48H8M32LFB5-75 IT:G is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). The MT48H8M32LFB5-75 IT:G provides for programmable read or write burst lengths (BLs) of 1, 2, 4, or 8 page locations with a read burst terminate option.

Parametrics

MT48H8M32LFB5-75 IT:G absolute maximum ratings: (1)Voltage on VDD/VDDQ supply relative to VSS (1.8V):–0.3 to +2.7V; (2)Voltage on inputs, NC or I/O balls relative to VSS (1.8V):–0.3 to +2.7V; (3)Storage temperature plastic:–55 to +150℃.

Features

MT48H8M32LFB5-75 IT:G features: (1)Fully synchronous; all signals registered on positive edge of system clock; (2)VDD/VDDQ = 1.70–1.95V; (3)Internal, pipelined operation; column address can be changed every clock cycle; (4)Four internal banks for concurrent operation; (5)Programmable burst lengths: 1, 2, 4, 8, or continuous page; (6)Auto precharge, includes concurrent auto precharge; (7)Auto refresh and self refresh modes; (8)LVTTL-compatible inputs and outputs; (9)On-chip temperature sensor to control refresh rate; (10)Partial-array self refresh (PASR); (11)Deep power-down (DPD); (12)Selectable output drive (DS); (13)64ms refresh period (8,192 rows).

Diagrams

MT48H8M32LFB5-75 IT:G block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
MT48H8M32LFB5-75 IT:G TR
MT48H8M32LFB5-75 IT:G TR


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Data Sheet

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