(China (Mainland))
Product Summary
The MT41J128M8JP-125:G DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The architecture of the MT41J128M8JP-125:G is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the MT41J128M8JP-125:G consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
Parametrics
MT41J128M8JP-125:G absolute maximum ratings: (1)VDD supply voltage relative to VSS: –0.4V to 1.975V; (2)VDD supply voltage relative to VSSQ: –0.4V to 1.975V ; (3)Voltage on any pin relative toVSS: -0.4V to 1.975V ; (4)operating case temperature: 0°C to 95°C; (5)storage temperature: -55°C to 150°C.
Features
MT41J128M8JP-125:G features: (1)VDD = VDDQ = +1.5V ±0.075V; (2)1.5V center-terminated push/pull I/O; (3)Differential bidirectional data strobe; (4)8n-bit prefetch architecture; (5)Differential clock inputs (CK, CK#); (6)8 internal banks ; (7)Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals; (8)CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11; (9)POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2; (10)CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK; (11)Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]); (12)Selectable BC4 or BL8 on-the-fly (OTF); (13)Self refresh mode; (14)TC of 0 to 95℃: 64ms, 8,192 cycle refresh at 0 to 85℃, 32ms at 85 to 95℃; (15)Clock frequency range of 300–800 MHz; (16)Self refresh temperature (SRT); (17)Automatic self refresh (ASR); (18)Write leveling; (19)Multipurpose register; (20)Output driver calibration.
Diagrams
| Image | Part No | Mfg | Description |  |
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 MT41J128M8JP-125:G |
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IC DDR3 SDRAM 1GBIT 78FBGA |
Data Sheet |
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