(China (Mainland))
Product Summary
The EDE5116AJBG-8E-E is a 512M bits DDR2 SDRAM. It must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The EDE5116AJBG-8E-E should be in all bank precharge with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register.
Parametrics
EDE5116AJBG-8E-E absolute maximum ratings: (1)Power supply voltage: -1.0 to +2.3V; (2)Power supply voltage for output: -0.5 to +2.3V; (3)Input voltage: -0.5 to +2.3V; (4)Output voltage: -0.5 to +2.3V; (5)Storage temperature: -55 to +100℃; (6)Power dissipation: 1.0W; (7)Short circuit output current: 50mA.
Features
EDE5116AJBG-8E-E features: (1)Double-data-rate architecture; two data transfers per clock cycle ; (2)The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture ; (3)Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver ; (4)DQS is edge-aligned with data for READs; center-aligned with data for WRITEs ; (5)Differential clock inputs (CK and /CK) ; (6)DLL aligns DQ and DQS transitions with CK transitions ; (7)Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS ; (8)Data mask (DM) for write data ; (9)Posted /CAS by programmable additive latency for better command and data bus efficiency ; (10)Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality ; (11)Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization ; (12)/DQS, (/RDQS) can be disabled for single-ended Data Strobe operation.
Diagrams
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